Mathematical Model of Energy Consumption of A Hierarchical Shared Bus Interconnection Communication Network of an On-Chip Multiprocessor

Energy consumption is one of the performance issues in multiprocessor design. Apart from being critical for power critical systems, it determines the amount of heat dissipates by the system. That is, as the energy consumption rate reduces heat dissipation reduces. Many research efforts had gone into the different design schemes for reducing multiprocessors’ energy consumption. However, it has been observed that there is a distinct relationship between energy consumed and the interconnection network engaged by the multiprocessors. In this paper, an energy consumption model was developed for a bus based interconnection network multiprocessor. The model established a linear relationship between bit energy of multiprocessor shared bus interconnection network and length of the bus covered during the bus cycle. This was used to obtain the maximum energy and bit energy consumed by the multiprocessor. The obtained bit energy (Pwbit) was compared with the bit energy of other interconnection networks in order to determine and evaluate the interconnection network which consumes least energy during bits transition. The bit energy obtained (2.45x1021 J) for the hierarchical shared bus interconnection network was much lower than the results reported for Crossbar (2.2 x 10-13 J), Banyan 2x2 (1.1 x 10-12 J), Batcher 2x2 (1.2 x 10-12 J), Banyan 4x4 (1.4 x 10-14 J), Banyan 16x16 (1.5 x 10-14 J) and Banyan 32x32 (2.2 x 10-14 J) interconnection networks. This indicates that the use of hierarchical shared bus interconnection network in the multiprocessor reduces its energy consumption. Keyword: Energy consumption; multiprocessor; interconnection network (IN); shared bus